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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD1818 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 617/329-4700 world wide web site: http://www.analog.com fax: 617/326-8703 ? analog devices, inc., 1997 preliminary technical data pci soundcomm ? dc 97 digital controller functional block diagram features single-chip 5 v pci digital controller for audio and communications acceleration applications 64-stream directsound ? hardware mixer with hardware rate conversion supports full duplex capture and playback operation at different sample rates supports multiple sample rates simultaneously sample rates from 1 hz to 48 khz windows ? 98 wdm ? drivers provided with the AD1818 digital ready pci bus redirection supports usb and ieee 1394 audio peripherals integrated large memory 66 mips adsp-21csp11 dsp core supports: 64-voice downloadable sounds wavetable synthesizer 3d sound localization 5.1 channel dolby digital ? ac-3 decompression with virtual home theater processing telephony applications v.34 and 56 kbps voice modem v.17 fax v.70 dsvd v.80 video conferencing support full duplex speakerphone with acoustic echo cancellation g.72x voice codecs serial interface to audio codec 97 (ac 97) support for up to four adcs and six dacs on the ac link serial bus pci bus master/target interface with scatter-gather dma capability on-chip opl3 ? compatible music synthesizer mpu-401 ? -compatible midi uart advanced power management modes and pme# signal support acpi, pcm-pm and on now ? 128-terminal pqfp package complete set of development tools available including ice, c compiler, assembler and debugger introduction the AD1818 5 v pci soundcomm dc 97 digital controller is a full-featured directsound and telephony accelerator. in addition to processing directsound3d ? coefficients locally, the AD1818 supports a 64-voice downloadable sounds wavetable engine, a music synthesizer, a 33.6 kbps v.34/56 kbps v.pcm voice modem data p ump/controller (with 14400 bps fax) and a dolby digital ac-3 decoder. the AD1818 provides an integrated audio and telephony sol ution for windows 98 directsound 5.0 audio/tapi ? telephony multimedia applications. soundcomm is a registered trademark of analog devices, inc. all other trademarks are the property of their respective holders. inta# pci bus interface clk rst# ad[31:0] par frame# trdy# irdy# stop# idsel devsel# req# gnt# perr# serr# c/be[3:0]# pme# music synthesizer clock oscillator dsp core mpu-401 midi uart mixer/ rate converter directsound ac link interface emulation interface modem/ phone line interface bit_clk sync sdata_in sdata_out reset# eck ems edi edo erst emu ring hook phone micena external i/o, interrupt input fifos dsp memory eeprom interface xctl[1:0] flag[1:0] dspint# midi_in midi_out scl sda
AD1818 C2C rev. 0 preliminary technical data ordering guide temperature package package model range description option* AD1818js 0 c to +70 c 128-terminal pqfp s-128a *s = plastic quad flatpack. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 4 architectural overview . . . . . . . . . . . . . . . . . . . . 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 integrating the AD1818 into a target system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 software driver support . . . . . . . . . . . . . . . . . . . . 7 audio sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 directsound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 directsound mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 extended directsound mixer . . . . . . . . . . . . . . . . . . . . . . 8 sample rate converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 music synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 mpu-401-compatible midi uart . . . . . . . . . . . . . . . 9 dsp section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dsp boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dsp interface registers . . . . . . . . . . . . . . . . . . . . 10 dma transfer count register . . . . . . . . . . . . . . . . . . . . . 10 dma control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 dsp mailbox registers . . . . . . . . . . . . . . . . . . . . . . . . . . 10 pci memory organization . . . . . . . . . . . . . . . . . . . . . . . . 10 wavetable music synthesis . . . . . . . . . . . . . . . . . . . . . . . 12 dsp to mixed fifos on the AD1818 . . . . . . . . . . . . . . . 12 warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD1818 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pci interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 the AD1818 logical device . . . . . . . . . . . . . . . . . . 14 scatter-gather dma on the AD1818 . . . . . . . . 14 pci configuration space organization for the AD1818 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 configuration space register definition . . 15 pci memory space register definition . . . . . 15 analog/digital interface . . . . . . . . . . . . . . . . . . 19 analog/digital ac 97 protocol . . . . . . . . . . . . . . . . . . . . 19 ac link audio output stream (sdata_out) . . . . . . . 19 ac link audio input stream (sdata_in) . . . . . . . . . . 20 analog codec interface control . . . . . . . . . . . . . . . . . . . . 21 electrical specifications . . . . . . . . . . . . . . . . . . 22 application circuits . . . . . . . . . . . . . . . . . . . . . . . . 26
AD1818 C3C rev. 0 preliminary technical data pin configuration 92 93 95 90 91 88 89 87 96 86 94 81 82 83 84 79 80 78 76 77 85 75 73 74 71 72 69 70 67 68 66 65 98 99 101 97 102 10 0 41 42 43 44 46 47 48 49 39 45 40 62 61 60 64 63 59 55 50 51 52 53 54 56 57 58 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 32 31 5 4 3 2 7 6 9 8 1 34 33 36 35 38 37 120 121 122 123 124 125 126 127 128 119 111 118 117 116 115 114 113 112 110 109 108 107 106 105 104 103 pin 1 identifier top view (not to scale) ad13 dgnd ad14 ad15 c/be1# par dvdd serr# perr# stop# devsel# dvdd dgnd trdy# dgnd irdy# frame# ad12 c/be2# ad16 dgnd xtali/clkin xtalo dvdd ad21 micena ad22 nc ad23 nc idsel nc c/be3# dvdd dvdd nc ad24 dgnd ad25 dvdd ad26 nc ad27 nc dgnd nc ad28 nc ad29 dgnd inta# nc pme# bit_clk sync sdata_in sdata_out reset# midi_in ad11 ad10 dvdd ad9 ad8 c/be0# ad7 dgnd ad6 ad5 ad4 ad3 dvdd ad2 ad1 ad0 nc dgnd dgnd dvdd scl sda emu erst# eck ems edi edo nc dvdd dspint# ring midi_out dgnd ad30 ad31 req# gnt# clk dvdd dgnd rst# dvdd AD1818js flag0 flag1 phone nc xctl0 xctl1 nc nc nc nc nc nc dvdd nc dgnd dgnd nc nc nc dvdd ad17 ad18 ad19 ad20 dgnd hook preliminary technical data
AD1818 C4C rev. 0 preliminary technical data pin function descriptions pci bus interface pin name pqfp i/o description clk 85 i clock rst# 82 i reset ad[31:0] 88, 89, 90, 91, 93, 94, 95, 96, 100, 101, 102, 104, 105, 106, 107, 109, 124, 125, 127, 128, 1, 2, 4, 5, 7, 9, 10, 11, 12, 14, 15, 16 i/o address/data bus c/be[3:0]# 98, 110, 123, 6 i/o command/byte enables par 122 i/o parity frame# 111 i/o cycle frame trdy# 114 i/o target ready irdy# 112 i/o initiator (master) ready stop# 118 i/o stop idsel 99 i initialization device select devsel# 117 i/o device select req# 87 o request gnt# 86 i grant perr# 119 i/o parity error serr# 120 o system error inta# 80 o interrupt a pme# 79 o power management event. signal changes in power management state. requested by AD1818, e.g., modem wake-up on ring. ac link pin name pqfp i/o description bit_clk 78 i serial clock sync 77 o frame sync sdata_in 76 i serial data out sdata_out 75 o serial data in reset# 74 o ac 97 reset midi interface pin name pqfp i/o description midi_in 73 i rxd midi input midi_out 72 o txd midi output emulation interface pin name pqfp i/o description eck 25 i emulator clock ems 26 i emulator mode select edi 27 i emulator data input edo 28 o emulator data output erst# 24 i emulator logic reset emu 23 o emulator event pin eeprom interface pin name pqfp i/o description scl 21 o serial clock sda 22 i/o serial data
AD1818 C5C rev. 0 preliminary technical data modem/phone line interface pin name pqfp i/o description ring 32 i ring indicator from daa hook 40 o on/off hook control to daa phone 35 i phone pickup indicator from daa micena 45 o microphone/line source select miscellaneous pin name pqfp i/o description xctl[1:0] 38, 37 o external controls flag[1:0] 34, 33 i input flags dspint# 31 i dsp interrupt crystal/clock pin name pqfp i/o description xtali/clkin 42 i 33 mhz crystal input/clock input xtalo 43 o 33 mhz crystal output power supplies/no connects pin name pqfp i/o description dgnd 8, 18, 19, 39, 41, 51, 57, 68, 71, 83, 92, 103, 113, 115, 126 i digital ground dvdd 3, 13, 20, 30, 44, 49, 52, 63, 81, 84, 97, 108, 116, 121 i +5 v digital supply voltage nc 17, 29, 36, 46, 47, 48, 50, 53, 54, 55, 56, no connect. do not connect. 58, 59, 60, 61, 62, 64, 65, 66, 67, 69, 70
AD1818 C6C rev. 0 preliminary technical data architectural overview figure 1 shows the functional blocks that make up the AD1818. the AD1818s design is focused to accelerate directsound and tele phony algori thms. the pci bus master/bus target interface provides the path for moving directsound data from host memory into the AD1818 for further acceleration. the 64-stream digital mixer and sample rate converters, combined with the internal dsp, accelerate mixing, sample rate conversion and 3d localiza- tion in hardware. the dsp may also be used to execute wavetable algorithms and dolby digital ac-3 decoding functions, and as a telephony data pump/controller. figure 2 shows a detailed view of the AD1818 internal structure. ac '97 link interface oscillator opl3 compatible music synthesizer engine 16k 16 16k 24 local memory 66 mips adsp-21csp11 dsp core master and target data fifos directsound digital mixer 16-channel sample rate converter rev.2.1 pci bus master/ target interface configuration space registers mpu-401 compatible midi uart figure 1. block diagram mixer/ac '97 register i/f sample rate conversion music synth legacy audio i/f direct sound i/f analog i/f pci dag pci register interface idma port fifo dsp i/f master slave mixer control input fifos data fifo primary secondary stereo adc stereo dac stereo dac rcv xmit mic spkr ac '97 reg i/f s h i f t 66 mips csp11 dsp core 16k 24 16k 16 dsp memory dsp mixer data register data audio or modem output to ac '97 only dsp xmit fifos output fifos pci bus pci i/f directsound hardware accelerator ac '97 i/f fifo s h i f t audio or handset audio handset modem audio handset modem audio or modem 2 dsp data dsp rcv fifos 32ds + 2dsp = 34 01 01 2 audio handset modem r e g r e g r e g serial input serial output figure 2. detailed block diagram
AD1818 C7C rev. 0 preliminary technical data integrating the AD1818 into a target system the system block diagram shows the essential features of an AD1818 design. the AD1818 acts as a master to the ac 97 audio codec providing digital processing for directsound audio data as well as communications data streams. the ac 97 industry standard codec interface provides a direct connection point for an ac 97 compatible codec such as the ad1819 from analog devices. audio i/o eeprom pci bus daa ad1819 ac '97 audio codec ad1819 ac '97 modem codec modem i/o daa control and status AD1818 digital controller ac-link midi i/o figure 3. system block diagram software driver support the AD1818 windows 98 directsound wdm drivers play a critical role in arbitrating AD1818 and system resources. any algorithm or acceleration function such as digital mixing may be locally processed on the AD1818, the host or a combination of both. a real-time operating system kernel runs on the dsp and performs several functions. these include: algorithm loading algorithm initialization algorithm execution algorithm termination AD1818 resource sharing (algorithm cooperation) real-time task scheduling and execution preemption clock and timer functions audio sources directsound the AD1818 contains a 64-stream digital mixer block for directsound buffers. four output channels are produced from the mixer, two of which are the primary audio left and right outputs. each of the four channels can be optionally transferred back to the host for further processing. dma controller a m a m a m a m l r l src dma controller a m a m a m a m r l src dma pci bus controller a m a m a m a m r l src dma controller a m a m a m a m r l src dma controller a m a m a m a m r l src dma controller a m a m a m a m r l src dma controller a m a m a m a m r l src dma controller a m a m a m a m r src analog interface primary secondary l r mixer data bus a = attenuate m = mute src = sample rate converter figure 4. basic directsound digital mixer and sample rate converters
AD1818 C8C rev. 0 preliminary technical data directsound mixer one of the principal features of directsound is mixing. most games open between three to eight sound buffers and mix them simultaneously. a buffer contains either a mono or a stereo source. when multiple sounds are mixed in software, cpu utilization increases and system latency may cause sounds and visual cues to become unsynchronized. in order to allow games to run faster and more smoothly, the AD1818 has a built- in hardware mixer capable of mixing and sample rate converting up to 64 digital streams. the stereo output of the mixer may be sent the analog interface, the dsp for digital processing as in directsound 3d and effects, or returned to the host via the pci bus. the AD1818s 32-channel pci dma controller interface transfers either 32 stereo channels (64 streams) or 32 mono streams into the hardware mixer. the dma controller directs the playing or stopping of a sample buffer and is capable of automatically looping to the start of a buffer. the dma controller counts the number of bytes transferred and can stop playing a sample after a specified number of bytes have been transferred. if the number of bytes is greater than the length of the buffer, the buffer automatically loops back to the beginning. after initiating a dma transfer, the sample data enters the AD1818 mixer. attenuation blocks (a) control the volume of a sample from 0 db to C94.5 db in 1.5 db steps for the left and right channel of each stream, or the stream can be completely muted (m). panning is supported by a combination of the left and right attenuation blocks, making the sound move across a sound field. the streams are then summed together in blocks of four. every four streams of left channel data (must be at the same sample rate) are summed together as well as every four streams of right channel data (same sample rate) producing eight separate samples of left and right data. the eight stereo samples then enter the sample rate converter block (src). eight independent programmable src blocks convert the summed samples from a user-specified sample rate to the ac 97 standard sample rate of 48 khz. the input sample rate ranges from 1 hz to 48 khz in 1 hz increments. the resulting left data may be returned to the mixer data bus or summed to produce one left output stream. right digital data may be returned to the mixer data bus or summed to produce one right output stream completing the stereo sample pair of the primary summer. the stereo output of the primary summer may be sent to either the mixer data bus or the analog interface. the secondary summer provides an additional stereo output for the mixer data bus, which may be sent to the dsp for effects processing or routed back to the pci bus. extended directsound mixer in addition to the AD1818s basic directsound mixer, an extended mixer and src stage handles streams sent to the mixer data bus from the dsp and the internal music synthesizer. the extended mixer allows for further processing and remixing of data. for example, data handled by the basic mixer may be sent to the dsp for effects processing and then mixed with the AD1818s output to generate effects such as echo and rever- beration or directsound3d. sample rate converter the sample rate converter (src) blocks attached to the basic and extended directsound audio streams are variable interpolating srcs. each converter accepts samples at the rate of 1 hz to 48 khz and interpolates the samples to a common rate of 48 khz. in addition, a variable decimation src is included to accept a single stereo channel of audio data at 48 khz and decimate the sample to any rate between 1 hz and 48 khz. utilizing analog devices variable sample rate technology, each src employs a scalable anti-aliasing or anti-imaging filter to properly filter the rate converted data. the result is a high performance multiple format and multiple sample rate mixer. given the high resolution of the srcs, the mixer can be used to accelerate the pitch shifting operation for digital effect or music analog interface primary secondary l r src src src mixer data bus music synthesizer dsp transmit fifo dsp transmit fifo basic direct sound mixer output figure 5. extended directsound digital mixer and sample rate converters
AD1818 C9C rev. 0 preliminary technical data generation. since the interpolated data has a C90 db snr performance, the pitch shifting performed by the srcs has no audible artifacts common in a lower quality pitch shifting algorithms. to shift the pitch, simply program the sample rate register of an audio stream to a different value. for example, to double the pitch of an 8 khz prerecorded audio sample, program the sample rate register to 16000. note that the valid range of the frequency register is 1 hz to 48000 hz. sampled data cannot be pitch shifted beyond 48 khz. the variable decimation src provides a means to reduce audio data storage size by reducing the sample rate cleanly. for example, a 10 second recording of stereo audio data can be acquired at the ac link as a 1.92 mbyte file, or resampled and reformatted in real time with the src to a 80 kbyte mono, m law compressed, 8 khz file. music synthesis the AD1818 includes an embedded music synthesizer that emulates industry standard opl3 fm synthesizer chips and delivers 20-voice polyphony. the internal synthesizer generates digital music data at 22.05 khz. the music synthesizers output is summed with the output stream. the music synthesizer on the AD1818 has register readback capability to facilitate power-down save and restore. the music synthesizer has been developed by euphonics, a research and development company that specializes in audio processing and electronic music synthesis. mpu-401-compatible midi uart the primary interface for communicating midi data to and from the host pc is the hardware mpu-401 compatible inter- face. the mpu-401 compatible interface includes a built-in fifo for communicating to the host bus. external eeprom pins scl and sda on the AD1818 are available to provide an interface to a serial eeprom. when a serial eeprom is connected to the AD1818, the subsystem vendor id and subsystem device id configuration space registers are loaded from the eeprom. loading of these registers occurs when the part exits reset. the four bytes are read starting at byte address 0, with the upper byte of the subsystem device id read first followed by the lower byte of the subsystem device id, upper byte of the subsystem vendor id and, lastly, the lower byte of the subsytem vendor id. the 2-wire interface requires serial eeproms such as the x24c01 from xicor. for the interface to be activated, external pullups are required on the scl and sda pins. if the scl pin is pulled low upon reset, then the interface is automatically disabled and the default values remain in the subsystem vendor id and subsystem device id registers. dsp section the dsp in the AD1818 is based on the analog devices adsp-21csp11 processor. please refer to the adsp-21csp11 concurrent signal processor data sheet (analog devices publication c2180-8-10/96) for additional information on the adsp-21csp11 core, memory and peripheral features and functions. this 16-bit dsp is optimized for concurrent signal processing and other high speed numeric processing applica- tions. it combines high performance, high bandwidth, 32k words of on-chip memory and fast task switching support to provide efficient multisignal or multichannel processing. the dsp base architecture consists of computational units, data address generators, a program sequencer and an instruction cache. the dsp on the AD1818 also has a programmable timer, exten- sive interrupt capabilities and 32k words of on-chip memory. the memory is organized into a single, unified memory space contain- ing two memory blocks with 16k locations in each block. one block is 16k 24 bits and can be used to store instructions or data, while the other is 16k 16 bits and can be used to store data. additions to the dsp for the AD1818 include a high speed dma interface to the pci bus. as a pci target, the dsp exposes its on-chip memory to the bus, allowing burst transfers via a fifo to or from the dsp memory. as a bus master, the pci interface can transfer dma data between system memory and the dsp. the control registers for these transfers are avail- able both to the host (in pci memory space) and to the dsp. five fifos have also been added to interface the dsp to the audio and telephony data streams on the AD1818. the two receive and three transmit fifos are each eight words deep and 16 bits wide. each fifo has independent control, allowing a dsp interrupt to be generated when any number of words have been added to or taken from the fifos. optionally, the on-chip dma engine can be programmed to automatically transfer data between the fifos and dsp memory. the dsp also has access to various control registers within the mixer and the analog interface. the on-chip dsp operates at 66 mhz with a 16 ns instruction cycle time. with its large memory and on-chip instruction cache, the processor can execute most instructions in a single cycle. the dsps flexible architecture and comprehensive instruction set supports a high degree of parallelism. in one cycle the dsp can execute all of the following operations: perform a computation perform one or two data moves update one or two data address pointers generate a program address fetch an instruction decode an instruction the operations take place while the processor continues to complete the following tasks: receive and transmit data through one or more of the fifos receive or transmit data from the pci bus decrement the timer dsp boot following power-up, the dsp core is held in idle, waiting to be booted. boot code is downloaded from the pci bus; there is no other method of booting the AD1818s dsp. during the boot code download process, the host is the pci bus master and the AD1818 is a slave target. the dsp memory is mapped to pci address space. this mapping is controlled through base address register 4 in AD1818 pci configuration space. this register controls the mapping of the on-chip 16k 24 dsp memory, which is nominally used for program memory. there is a separate register (base address register 5 in AD1818 pci configuration space) that maps the on-chip 16k 16 dsp memory, nominally used for data memory. after the host is finished filling the dsp with boot code, the host must set the clear dsp boot mode (bit 3) in the dsp dma control register (offset 0x1803-0x1802 from the AD1818 base
AD1818 C10C rev. 0 preliminary technical data address). setting this bit takes the dsp out of idle, and causes the dsp to start program execution from location 0x0000. dsp interface registers dma transfer count register a 16-bit register contains the number of words to be transferred between pci address space and the dsp internal memory. the word size refers to the width of transfers into the dsp internal memory. the word width may be 32 bits or 16 bits, depending on the state of the dsp pack mode bit in the dsp control register. when the transfer count register reaches zero during a dma transfer, the dma channel is disabled. the transfer count register must be manually reinitialized before another dma transfer may begin. dma control register this register contains bits used to control and observe the state of dma transfers to the dsp core. the con trol bits are read/write bits. the status bits are read-only. control bits bit # description 0 master dma enable. when asserted enables, pci master dma on the dsp dma channel. must be toggled off, then on to restart when dma is disabled via the pci address generation logic or the transfer count register. 1 master dma write/not read. when asserted, speci- fies dma to write to pci address space. 2 flush master dma fifo. when asserted, discards the current contents of the dma master fifo and associ- ated logic. 3 clear dsp boot mode. when asserted, forces the dsp core to begin executing instructions from the dsp inter- nal memory. this function is valid after dsp reset. 4 master dma pack mode. specifies the dsp internal word width for dma transfers (1 = 32-bit words). this bit alters the semantics of the transfer count register. 5 d3 state power-down enable. when set, allows a change to pci power management state d3 to put the AD1818 into power-down. 6C7 reserved. status bits bit # description 8 master dma fifo empty. this bit is set to one when there is no data is in the master dma channel fifo or packing logic. 9 master dma halt status. this bit is set to one when the master dma channel is disabled by the pci ad- dress generation logic. 15C10 reserved dsp mailbox registers the dsp mailbox registers are designed to allow the user to construct an efficient communications protocol between the pci device driver and the dsp code. the mailbox functions consist of an inbox, outbox and a control/status register. inbox the incoming mailbox (inbox) is 32 bits wide. it may be read or written by either the pci device or the dsp core. the pci device may access any or all bytes at one time. the dsp core may only access 16 bits at one time. pci writes to the inbox may generate dsp interrupts. dsp reads of inbox may generate pci interrupts. outbox the outgoing mailbox (outbox) is 32 bits wide. it may be read or written by either the pci device or the dsp core. the pci device may access any or all bytes at one time. the dsp core may only access 16 bits at one time. dsp writes to the outbox may generate pci interrupts. pci reads from the outbox may generate dsp interrupts. control/status this register consists of read/write control bits and read/ write-one-clear status bits (denoted r/w and r/wc respec- tively). a read/write-one-clear (r/wc) bit is cleared when a one is written to it. writing a zero has no effect. bit # type description 3C0 r/wc inbox byte data valid. a one in these bits means valid data has been written into the corresponding inbox bytes. the bits are cleared when they are written with ones, or when inbox is read. 7C4 r/wc outbox byte data valid. a one in these bits means valid data has been written into the corresponding outbox bytes. the bits are cleared when they are written with ones, or when outbox is read. 11C8 r/o reserved. 12 r/wc inbox pci interrupt pending. this bit is set when the dsp reads valid data from the inbox. 13 r/wc outbox pci interrupt pending. this bit is set when the dsp writes valid data to the outbox. 14 r/wc inbox dsp interrupt pending. this bit is set when the pci writes valid data to the inbox. 15 r/wc outbox dsp interrupt pending. this bit is set when the pci reads valid data from the outbox. 16 r/w inbox pci interrupt enable. when asserted, allows the corresponding interrupt pending bit to be set. 17 r/w outbox pci interrupt enable. when asserted, allows the corresponding interrupt pending bit to be set. 18 r/w inbox dsp interrupt enable. when asserted, allows the corresponding interrupt pending bit to be set. 19 r/w outbox dsp interrupt enable. when as serted, allows the corresponding interrupt pending bit to be set. 31C20 reserved. pci memory organization as mentioned above, the AD1818 on-chip memory is mapped to the pci address space. because one of the AD1818 memory
AD1818 C11C rev. 0 preliminary technical data blocks is 24 bits wide, and the other AD1818 memory block is 16 bits wide, there are two different footprints in pci address space. the 16k by 24-bit dsp memory requests 128k bytes of nonpacked pci memory. of this, 64k bytes are reserved (for larger memory versions of the AD1818 in the future), 48k bytes are used and 16k bytes are unused. this footprint is illustrated in figure 6. the 16k by 16-bit dsp memory requests 64k bytes of packed pci memory. of this, 32k bytes are reserved (for larger memory versions of the AD1818 in the future) and 32k bytes are used. this footprint is illustrated in figure 7. internal dsp i/o access addresses i/o page address directsound mixer control register 0 0x00 dma input channel 0C3 mixer control 0 0x02 dma input channel 4C7 mixer control ... 0 0x0e dma input channel 28C31 mixer control 0 0x1eC0x10 reserved 0 0x22C0x20 dma input channel enable register 0 0x3eC0x24 reserved 0 0x40 dma output channel 0 mixer control 0 0x42 dma output channel 1 mixer control ... 0 0x46 dma output channel 3 mixer control 0 0x48 dma output channel enable register 0 0x7eC0x4a reserved 0 0x80 reserved 0 0xffC0x82 reserved 1 0x00 dma input channel 0 attenuation 1 0x02 dma input channel 1 attenuation ... 1 0x3e dma input channel 31 attenuation 1 0x40 reserved 1 0x42 reserved 1 0x44 dsp output channel 0 attenuation 1 0x46 dsp output channel 1 attenuation 1 0x48 music synthesis attenuation 1 0x4a ac 97 mic input attenuation 1 0x4c ac 97 audio input attenuation 1 0x4e reserved 1 0x7eC0x50 reserved 1 0x80 mixer channel 0 input sample rate 1 0x82 mixer channel 1 input sample rate ... 1 0x8e mixer channel 7 input sample rate 1 0x90 reserved 1 0x92 reserved 1 0x94 dsp channel 0 input sample rate 1 0x96 dsp channel 1 input sample rate 1 0x98 reserved 1 0x9cC0x9a reserved 1 0x9e reserved 2 0x00 audio output channel select register 2 0x02 host/dsp output channel select register 2 0x1eC0x04 reserved 2 0x20 output channel 0 (variable output) sample rate 9C3 0xfeC0x00 reserved a 0x43C0x40 dsp dma output channel base address/ sgd table pointer a 0x47C0x44 dsp dma output channel current address/sgd cur pointer address a 0x4bC0x48 dsp dma output channel base count/ sgd pointer a 0x4eC0x4c dsp dma output channel current count a 0xfeC0x50 reserved cCb reserved d 0x22C0x20 dsp dma output channel interrupt count d 0x26C0x24 dsp dma output channel interrupt base count d 0xfeC0x24 reserved f 0x18C0x00 reserved f 0x22C0x20 dsp dma output channel pci control status f 0xffC0x24 reserved 0x0000 0000 offset 0x0000 0004 0x0000 8000 0x0000 8004 0x0000 fffc 0x0000 7ffc byte 3 byte 2 byte 1 byte 0 used used used reserved reserved reserved reserved reserved reserved reserved reserved 31 24 23 16 15 8 7 0 pci address space reserved reserved reserved reserved used used used used used used used used figure 7. footprint of AD1818 packed 16k 16 dsp memory in pci address space byte 3 byte 2 byte 1 byte 0 used used used unused used used used unused reserved reserved reserved reserved reserved reserved reserved reserved 31 24 23 16 15 8 7 0 pci address space reserved reserved reserved reserved 0x0000 0000 offset 0x0000 0004 0x0001 0000 0x0001 0004 0x0001 fffc 0x0000 fffc figure 6. footprint of AD1818 unpacked 16k 24 dsp memory in pci address space
AD1818 C12C rev. 0 preliminary technical data user0 C pci d1 power-up. connected to the pci power management control. used to bring the dsp out of idle while in the d1 power state. flagin0C1 C general purpose signals from pins. flagin3 C ring. see above. brought to flagin for ring counting. flagin2 C phone. from daa. flagin4 C reserved. flagin5 C analog interface ready. signals that the analog front-end is ready. flagin6C7 C reserved. flagout0C1 C general purpose signals to output pins. flagout2 C hook. signal to daa to connect to phone line. can be used as a general purpose pin output signal. flagout3 C m icenb. signal to enable microphone. can be used as a general purpose pin output signal. flagout4 C pme power-up request. signal to request a pme event on the pci bus to wake up the bus. a pme event will occur if the pme_en bit is set in the pci configuration pmcsr register and this signal is asserted. flagout5C7 C reserved. table i. interrupt vector table for the AD1818 bit pri interrupt vector address 0 1 reset (nonmaskable) 0x00 1 2 power-down (nonmaskable) 0x04 2 3 user interrupt 3 0x08 3 4 pci mailbox (irq3) 0x0c 4 5 timer 0x10 5 6 user interrupt 2 0x14 6 7 ring (irq2) 0x18 7 8 idma 0x1c 8 9 irq1 0x20 9 10 fifo0 transmit 0x24 10 11 fifo0 receive 0x28 11 12 fifo1 transmit 0x2c 12 13 fifo1 receive 0x30 13 14 48 khz sync (irq0) 0x34 14 15 fifo2 transmit 0x38 15 16 pci d1 power-up (user 0) 0x3c dsp to mixer fifos on the AD1818 five fifos provide an interface on the AD1818 between the dsp and the mixer data bus in the AD1818 core. two of the fifos are inputs fifos, receiving data from the mixer data bus into the dsp. the other three fifos are transmit fifos, sending data from the dsp to the mixer. each of the fifos are eight words deep and 16 bits wide. interrupts to the dsp can be generated when some (programmable) number of words have been received in the input fifos or when some (programmable) number of words are empty in the transmit fifos. the interface to the fifos on the dsp is simply a register interface to the idmd bus. tx0, rx0, tx1, and rx1 are the primary fifo registers in the universal register map of the dsp. stctl0-2, srctl0-1, tx2 and abfctl0-2 are the fifo control registers and are located in the memory-mapped register space of the dsp. the fifos can be used to generate interrupts to the dsp based upon fifo transactions or can initiate dma ac 97 interface registers page address register 10 0x7eC0x00 register set 10 0x80 analog codec interface control/status 17C11 reserved dsp control registers page address register 18 0x00 dma transfer count 18 0x02 dma control 18 0x06C0x04 mailbox control/status 18 0x0aC0x08 incoming mailbox 18 0x0eC0x0c outgoing mailbox wavetable music synthesis wavetable music synthesis algorithms are run on the internal dsp. the software wavetable engine will perform the necessary pitch shifting and envelope generation prior to mixing the channel back into the output streams. system (pci) memory is used for the storage of wavetable samples while the wavetable engine is in use. during application initializa- tion, the wavetable driver will load the wavetable samples into memory for use by the AD1818. the samples need not be in contiguous memory; instead, they will be accessed by the AD1818 via scatter-gather dma transfers. the standard dls download- able sounds format is supported by the AD1818 wavetable driver. the AD1818 wavetable driver provides all of the control required for the chip to perform the necessary sample rate conversion, envelope generation and effects processing. this includes midi command interpretation, location of note samples in memory and passing parameters to the AD1818 for note events. the wavetable synthesizer has been developed by euphonics, a research and development company that specializes in audio processing and electronic music synthesis. interrupt structure various flag input and output and interrupt pins within the dsp core are assigned to particular functions within the AD1818. the assignments are as follows: pwd C power-down interrupt. connected to bit in the pci dsp control register. irq3 C pci mailbox interrupt. writing to the incoming mailbox register or reading from the outgoing mailbox register via the pci bus can generate this interrupt. irq2 C ring. connected to the ring pin on the AD1818. this is an active-high interrupt. also connected without inversion to flagin[3]. used to connect to the ring signal from the daa for modem operation. if modem is not used, can be a general purpose interrupt. irq1 C connected to external pin. general purpose interrupt. irq0 C 48 khz sync. connects AD1818 dsp core to the start of frame signal. used to time data transfers to the core for audio effects. user1 C f ifo2 transmit. connected to the transmit interrupt for the third, transmit-only fifo. eusynth-1+ eusynth-1+ e u p honics
AD1818 C13C rev. 0 preliminary technical data requests. fifo2 uses the dma3 controller and the user-1 (#14) dsp interrupt. the interface to the fifos on the mixer side is via the mixer address and data bus. each of the transmit fifos is assigned two addresses on the mixer bus, one for left data and one for right data. upon reset or when the transmit fifo is disabled, zeros are driven to the mixer bus when the fifo is addressed. when the fifo is in mono mode, both left and right will get the same data. fifo2 always transmits stereo data. if the transmit fifos run out of data then the last data shipped will continue to be sent when addressed. the transmit fifos can also be used to ship data to the modem output on the analog codec (ac 97) interface. when modem mode is enabled in the transmit fifo, it responds to the modem_out address on the mixer data bus instead of the dsp_in addresses (this applies to fifo0 or fifo2 only). zeros are shipped to the mixer in modem mode. handset audio is handled similarly. while fifo0 or fifo2 support modem_out, fifo1 handles handset_out. on the receive side, the receiver will respond to addresses that are programmed into its receive control register. thus the receive fifos can collect any of the data that is sent on the mixer data bus. if stereo is enabled in the receive fifos, then both left and right data will be collected. in mono mode, only the left data will be collected. the data input can be from any of the rate converted output streams or from the analog codec (ac 97) interface. table ii shows the register format for each fifo. table ii. stctl0/1 transmit control and status register bit function when bit set to 1 0 tx enable 1 tx stereo enable 2 modem output enable on mixer channel 36 (fifo0) handset/speaker output enable on channel 54 (fifo1) 3 reserved . . . bits 4 through 11 reserved 12 reserved 13 transmit fifo full (read only) 14 transmit fifo empty (read only) 15 transmitter empty (read only) default state after reset: 0x00 stctl2 transmit-only fifo control and status register bit function when bit set to 1 0 tx enable (by itself: enables channels 44/45) 1 reserved 2 modem output enable (on channel 36) 3 4-channel (with tx enable, enables channels 46/47) 4 6-channel (with tx enable, enables channels 52/53) 5 reserved . . . bits 6 through 11 reserved 12 reserved 13 transmit fifo full (read only) 14 transmit fifo empty (read only) 15 transmitter empty (read only) default state after reset: 0x00 srctl0/1 transmit-only fifo c ontrol and s tatus register bit function when bit set to 1 0 rx enable 1 rx stereo enable 2 rx select address (lsb) 3 rx select address 4 rx select address 5 rx select address 6 rx select address (msb) 7 reserved . . . bits 8 through 11 reserved 12 reserved 13 receive fifo full (read only) 14 receive fifo empty (read only) 15 receiver full (read only) default state after reset: 0x00 abfctl0/1 dma and fifo control register bit function when bit set to 1 0 tx fifo enable 1 rx fifo enable 2 reserved 3 reserved 4 tx fifo interrupt position (lsb) 5 tx fifo interrupt position 6 tx fifo interrupt position (msb) 7 reserved 8 rx fifo interrupt position (lsb) 9 rx fifo interrupt position 10 rx fifo interrupt position (msb) 11 reserved 12 tx dma enable 13 reserved 14 rx dma enable 15 reserved default state after reset: 0x00 abfctl2 dma and fifo control register bit function when bit set to 1 0 tx fifo enable 1 reserved 2 reserved 3 reserved 4 tx fifo interrupt position (lsb) 5 tx fifo interrupt position 6 tx fifo interrupt position (msb) 7 reserved . . . bits 8 through 10 reserved 11 reserved 12 tx dma enable 13 reserved 14 reserved 15 reserved the fifos also use the dsp core registers tx buffer and rx buffer. fifo2s tx register is a sysctll register, reg (0xla) = reg(tx2). there is a total of 4 memory-mapped registers per dsp serial port (sport).
AD1818 C14C rev. 0 preliminary technical data directsound output channel to select channel matching select data stream transaction source data source 0 ds[0] rate converter/48 khz rate converter 1 ds[1] rate converter/48 khz rate converter 2 ds[2] rate converter/48 khz rate converter 3 ds[3] rate converter/48 khz rate converter 4 ds[4] rate converter/48 khz rate converter 5 ds[5] rate converter/48 khz rate converter 6 ds[6] rate converter/48 khz rate converter 7 ds[7] rate converter/48 khz rate converter 8 reserved 9 reserved a dsp_out[0] rate converter/48 khz rate converter b dsp_out[1] rate converter/48 khz rate converter c music synth rate converter/48 khz rate converter d var_out rate converter/variable rate converter e audio out rate converter/48 khz rate converter f hdsp_out rate converter/48 khz rate converter 10 audio_in ac 97/48 khz ac 97 11 modem_in ac 97/variable ac 97 12 modem_out ac 97/variable ac 97 13 mic_in ac 97/variable ac 97 14 dsp_from[0] rate converter/variable dsp 15 dsp_from[1] rate converter/variable dsp 16 dsp_2_acif[0] ac 97/variable dsp 17 dsp_2_acif[1] ac 97/variable dsp 18 reserved 19 reserved 1a dsp_2_acif[2] ac 97/variable dsp 1b handset ac 97/ variable dsp 1c music synth_in rate converter/22.05 khz music synthesizer 1d reserved 1e reserved 1f reserved pci interface in order to support the high data throughput required for concurrent audio and telephony algorithms, the AD1818 includes a 33 mhz, 32-bit bus master 5 v pci interface. the interface is compliant with revision 2.1 of the pci specification, and the AD1818 is memory-mapped to the pci bus. the AD1818 logical device the directsound mixer block provides the pci interface necessary for the 64-stream mixer block. this interface supports the use of system memory for storage of wavetable samples and envelopes. on-chip fifos provide the buffering needed to support high throughput on the pci bus and samples as needed for the wavetable synthesizer. scatter-gather capability is provided for each dma channel. a midi mpu-401 interface to the midi in and midi out pins is also provided by this logical device. the ac 97 interface is the primary interface to the main analog codec front-end. a fifo buffers data to and from the serial codec interface. the pci interface to the on-chip dsp provides both master and slave burst capability between system memory and the on-chip dsp memory. separate target addressing is provided for the 24-bit dsp program memory space and the 16-bit dsp data memory space. bus master dma can be controlled by either the dsp through an internal interface or the host via the pci inter- face. separate data fifos exist for target and master transfers. scatter-gather dma on the AD1818 when direct memory access (dma) is active, it will steal one cycle from the dsp core for each transfer that takes place. during the dma transfer, no other dsp core activity occurs. when transferring audio samples to the wavetable engine or the codec engine, the dma transfer can be programmed to perform scatter-gather dma. this mode allows the audio samples to be split up in memory, and yet able to be transferred to and from the AD1818 without processor intervention. in scatter-gather mode, the dma controller can read the memory address and word count from an array of buffer descriptors called the scatter-gather descriptor (sgd) table. this allows the dma engine to sustain dma transfers until all buffers in the scatter- gather descriptor table are transferred. to initiate a scatter-gather transfer between memory and the AD1818, the following steps are involved: 1. software driver prepares a sgd table in system memory. each scatter-gather descriptor (sgd) is eight bytes long and con- sists of an address pointer to the starting address and the trans- fer count of the memory buffer to be transferred. in any given sgd table, two consecutive sgds are offset by eight bytes and are aligned on a 4-byte boundary. each sgd contains: a. memory address (buffer start) C 4 bytes b. byte count (buffer size) C 3 bytes c. end of linked list (eol) C 1 bit (msb) d. flag C 1 bit 2. initialize dma control registers with transfer specific information such as bit width, compression mode, etc. 3. software driver initializes the hardware pointer to the sgd table. 4. engage scatter-gather dma by writing the start value to the scatter-gather command register. 5. the AD1818 will then pull in samples as pointed to by the scatter-gather descriptors as needed by the audio synthesis engine. when the end of linked list (eol) is reached, a status bit will be set and the dma will end if the sample is not to be looped. if looping is to occur, dma transfers will continue from the beginning of the sample until a stop command is received in the scatter-gather command register. 6. bits in the scatter-gather command register control whether or not an interrupt occurs when the end of linked list is reached or when the flag bit is set. pci configuration space organization for the AD1818 the AD1818 contains a single configuration space with six separate address spaces pointed to by address registers in that configuration space. the function is logical device 0. all of the AD1818 address spaces (including the configuration space) are memory-mapped to the pci bus.
AD1818 C15C rev. 0 preliminary technical data configuration space register definition configuration space register map address register comments 0x01C0x00 vendor id hardwired C 0x11d4 0x03C0x02 device id hardwired C 0x1818 0x05C0x04 command register reset to 0, see note (a) 0x07C0x06 status register see note (b) 0x08 revision id hardwired C 0x00 0x0b-0x09 class code hardwired C 0x040100 0x0c cache line size unimplemented 0x0d latency timer r/w, reset to 0 0x0e header type hardwired to 0 0x0f bist unimplemented 0x13C0x10 base address 0 8k bytes prefetchable directsound, codec, dsp registers 0x17C0x14 base address 1 16 bytes nonprefetchable music synthesis registers 0x1bC0x18 base address 2 16 bytes nonprefetchable midi mpu-401 interface 0x1fC0x1c base address 3 16 bytes nonprefetchable legacy control interface 0x23C0x20 base address 4 128k bytes prefetchable 24-bit dsp memory 0x27C0x24 base address 5 64k bytes prefetchable. 16-bit dsp memory 0x2bC0x28 cardbus cis pointer unimplemented 0x2dC0x2c subsystem vendor id reset to 0x11d4 0x2fC0x2e subsystem id reset to 0x1818 0x33C0x30 expansion rom unimplemented base address 0x34 capability pointer hardwired C 0xdc 0x3bC0x35 reserved in pci spec unimplemented 0x3c interrupt line r/w, reset to 0 0x3d interrupt pin hardwired C 0x01 (uses inta#) 0x3e min_gnt register hardwired C 0x01 0x3f max_lat register hardwired C 0x0a 0xdbC0x40 unimplemented 0xdc capability id hardwired C 0x01 0xdd next_cap_ptr hardwired C 0x00 0xdfC0xde power management cap hardwired C 0x1321 0xe1C0xe0 power mgmt. ctrl/stat reset to 0 0xe2 power mgmt. bridge hardwired to 0 0xe3 power mgmt. data hardwired to 0 0xffC0xe4 configuration space configuration space notes (a) command register bits: 0 C i/o space enable hardwired to 0, all accesses are via memory space 1 C memory space enable reset to 0 2 C bus master enable reset to 0 3 C special cycle enable hardwired to 0 4 C mwi enable unimplemented, hardwired to 0 5 C vga palette snoop unimplemented, hardwired to 0 6 C parity error response reset to 0 7 C address/data stepping hardwired to 0 8 C serr# enable reset to 0 9 C fast back-to-back reset to 0 15C10 hardwired to 0 ( b) status register bits: 3C0 hardwired to 0 4 C capabilities list hardwired to 1 5 C 66 mhz capable hardwired to 0 6 C udf supported hardwired to 0 7 C fast b2b capable hardwired to 1 8 C data parity error detect implemented, reset to 0 10C9 C devsel timing hardwired to 01 C medium speed 11 C signaled target abort implemented, reset to 0 12 C received target abort implemented, reset to 0 13 C received master abort implemented, reset to 0 14 C signaled system error implemented, reset to 0 15 C detected parity error implemented, reset to 0 unimplemented configuration space reads back 0s onto the pci bus if accessed, by default. pci writes to these locations have no effect. pci memory space register definition top-level base address offsets: directsound C offset from base address 0: address register 0x07ffC0x0000 mixer control registers 0x0fffC0x0800 dma registers 0x17ffC0x1000 ac 97 interface registers 0x1fffC0x1800 dsp control registers music synthesis C offset from base address 1: address register 0x00 opl3 music0: address (w), status (r) 0x01 opl3 music0: data 0x02 opl3 music1: address (w) 0x03 opl3 music1: data 0x0fC0x04 reserved midi mpu-401 C offset from base address 2: address register 0x00 midi data (r/w) 0x01 midi uart status (r), command (w) 0x0fC0x02 reserved legacy control C offset from base address 3: address register 0x00 legacy audio control/status. 0x0fC0x01 reserved dsp port C offset from base address 4: address register 0x1ffffC0x00 24-bit dsp memory dsp port C offset from base address 5: address register 0xffffC0x00 16-bit dsp memory
AD1818 C16C rev. 0 preliminary technical data base address 0 register detail: directsound mixer control registers address register 0x001C0x000 dma input channel 0C3 mixer control 0x003C0x002 dma input channel 4C7 mixer control . . . 0x00f dma input channel 28C31 mixer control 0x01fC0x010 reserved 0x023C0x020 dma input channel enable register 0x03fC0x024 reserved 0x041C0x040 dma output channel 0 mixer control . . . 0x047C0x046 dma output channel 3 mixer control 0x049C0x048 dma output channel enable register 0x0ffC0x04a reserved 0x101C0x100 dma input channel 0 attenuation 0x103C0x102 dma input channel 1 attenuation . . . 0x13fC0x13e dma input channel 31 attenuation 0x143C0x140 reserved 0x145C0x144 dsp output channel 0 attenuation 0x147C0x146 dsp output channel 1 attenuation 0x149C0x148 opl3 music synthesis attenuation 0x14bC0x14a ac 97 mic input attenuation 0x14dC0x14c ac 97 audio input attenuation 0x17fC0x14e reserved 0x181C0x180 mixer channel 0 input sample rate 0x183C0x182 mixer channel 1 input sample rate . . . 0x18fC0x18e mixer channel 7 input sample rate 0x193C0x190 reserved 0x195C0x194 dsp channel 0 input sample rate 0x197C0x196 dsp channel 1 input sample rate 0x19fC0x198 reserved 0x201C0x200 audio output channel select register 0x203C0x202 host/dsp output channel select register 0x21fC0x204 reserved 0x221C0x220 output channel 0 (variable output) sample rate 0x7ffC0x222 reserved directsound dma registers address register 0x803C0x800 dma input channel 0 base address / sgd table pointer 0x807C0x804 dma input channel 0 current address / sgd cur pointer address 0x80bC0x808 dma input channel 0 base count / sgd pointer 0x80fC0x80c dma input channel 0 current count 0x813C0x810 dma input channel 1 base address / sgd table pointer 0x817C0x814 dma input channel 1 current address / sgd cur pointer address 0x81bC0x818 dma input channel 1 base count / sgd pointer 0x81fC0x81c dma input channel 1 current count . . . 0x9f3C0x9f0 dma input channel 31 base address / sgd table pointer 0x9f7C0x9f4 dma input channel 31 current address / sgd cur pointer address 0x9fbC0x9f8 dma input channel 31 base count / sgd pointer 0x9ffC0x9fc dma input channel 31 current count 0xa03C0xa00 dma output channel 0 base address / sgd table pointer 0xa07C0xa04 dma output channel 0 current address / sgd cur pointer address 0xa0bC0xa08 dma output channel 0 base count / sgd pointer 0xa0fC0xa0c dma output channel 0 current count . . . 0xa33C0xa30 dma output channel 3 base address / sgd table pointer 0xa37C0xa34 dma output channel 3 current address / sgd cur pointer address 0xa3bC0xa38 dma output channel 3 base count / sgd pointer 0xa3fC0xa3c dma output channel 3 current count 0xa43C0xa40 dsp dma output channel base address / sgd table pointer 0xa47C0xa44 dsp dma output channel current address / sgd cur pointer address 0xa4bC0xa48 dsp dma output channel base count / sgd pointer 0xa4fC0xa4c dsp dma output channel current count 0xbffC0xa50 reserved 0xc02C0xc00 dma input channel 0 interrupt count 0xc03 reserved 0xc06C0xc04 dma input channel 0 interrupt base count 0xc07 reserved 0xc0aC0xc08 dma input channel 1 interrupt count 0xc0b reserved 0xc0eC0xc0c dma input channel 1 interrupt base count 0xc0f reserved . . . 0xcfaC0xcf8 dma input channel 31 interrupt count 0xcfb reserved 0xcfeC0xcfc dma input channel 31 interrupt base count 0xcff reserved 0xd02C0xd00 dma output channel 0 interrupt count 0xd03 reserved 0xd06C0xd04 dma output channel 0 inte rrupt base count 0xd07 reserved . . . 0xd1aC0xd18 dma output channel 3 interrupt count 0xd1b reserved 0xd1eC0xd1c dma output channel 3 interrupt base count 0xd1f reserved 0xd22C0xd20 dsp dma output channel interrupt count 0xd23 reserved 0xd26C0xd24 dsp dma output channel interrupt base count 0xd27 reserved 0xdffC0xd28 reserved 0xe03C0xe00 dma input channel 0 pci control/status 0xe07C0xe04 reserved 0xe0bC0xe08 dma input channel 1 pci control/status 0xe0fC0xe0c reserved . . . 0xefbC0xef8 dma input channel 31 pci control/status 0xeffC0xefc reserved 0xf03C0xf00 dma output channel 0 pci control/status
AD1818 C17C rev. 0 preliminary technical data 0xf07C0xf04 reserved . . . 0xf1bC0xf18 dma output channel 3 pci control/status 0xf1fC0xf1c reserved 0xf23C0xf20 dsp dma output channel pci control/status 0xf27C0xf24 reserved 0xf7fC0xf28 reserved 0xf83C0xf80 dma interrupt register 1 0xf87C0xf84 dma interrupt register 2 0xf8bC0xf88 dma channel stop status register 1 0xf8fC0xf0c dma channel stop status register 2 0xfffC0xf90 reserved ac 97 codec interface registers address register 0x107fC0x1000 ac 97 register set 0x1081C0x1080 analog codec interface control/status 0x17ffC0x1082 reserved dsp control registers address register 0x1801C0x1800 dma transfer count 0x1803C0x1802 dma control 0x1807C0x1804 mailbox control/status 0x180bC0x1808 incoming mailbox 0x180fC0x180c outgoing mailbox control register definitions: dma input channel mixer control registers (8) : bit # description 3C0 even channel data format 7C4 odd channel data format 31C8 reserved data format definition: bit # description 0 s/m C stereo/mono select (mono = 0, stereo = 1) 1 c/l C companded/linear select (linear = 0, companded = 1) 2 fmt C format select ( m -law/8-bit data = 0, a-law/16-bit data = 1) 3 reserved dma input channel enable register (1): bit # description 0 input channel 0 enable 1 input channel 1 enable . . . 31 input channel 31 enable output channel mixer control registers (4): bit # description 3C0 channel data format 7C4 reserved 12C8 mixer output select 16C13 reserved data format definition is defined above. mixer output select is a 5-bit value, which selects one channel as follows: directsound channel 0 0 directsound channel 1 1 . . . directsound channel 7 7 reserved 8 reserved 9 dsp fifo 0 10 dsp fifo 1 11 opl3 music synthesis 12 output channel 0 13 AD1818 audio output (primary) 14 AD1818 host/dsp output (secondary) 15 ac 97 audio in 16 ac 97 modem in 17 ac 97 modem out 18 ac 97 mic in 19 reserved 20C31 dma output channel enable register (1): bit # description 0 output channel 0 enable 1 output channel 1 enable . . . 3 output channel 3 enable 15C4 reserved channel attenuation registers (37): bit # description 5C0 left attenuation 6 reserved 7 left mute 13C8 right attenuation 14 reserved 15 right mute each channel attenuation bit is weighted 1.5 db. mixer/dsp input/output sample rates (10): sample rate (16 bits) output channel select register (2): bit # description 7C0 mixer output selects 8 reserved 9 reserved 10 dsp fifo 0 select 11 dsp fifo 1 select 12 opl3 music synthesis select 13 ac 97 mic input select 14 ac 97 audio input select 15 reserved output channel 0 sample rate (1): sample rate (16 bits)
AD1818 C18C rev. 0 preliminary technical data dma channel pci control/status registers: bit # description 0 sgd enable 1 loop enable 3C2 interrupt mode: 00 interrupt disabled 01 interrupt on count 10 interrupt on sgd flag 11 interrupt on eol 5C4 current sgd valid 00 full sgd descriptor needed (software must initialize this value) 01 partial sgd descriptor fetched 10 sgd valid 11 reserved (invalid status) 6 flag bit set in current sgd 7 eol bit set in current sgd dma interrupt register 1 bit # description 0 dma input channel 0 interrupt 1 dma input channel 1 interrupt . . . 31 dma input channel 31 interrupt dma interrupt register 2 bit # description 0 dma output channel 0 interrupt 1 dma output channel 1 interrupt 2 dma output channel 2 interrupt 3 dma output channel 3 interrupt 4 dsp dma channel interrupt 13C5 reserved 14 pci target abort interrupt 15 master abort interrupt 16 pci target abort interrupt enable 17 master abort interrupt enable 31C18 reserved dsp dma control register definition bit # description 0 dma enable 1 dma write/ read 2 flush master fifo 3 clear dsp boot mode 4 dma packing enable 5 d3 power-down enable 7C6 reserved 8 dma channel halt status (1 = halt) 9 dma fifo empty status (1 = empty) 15C10 reserved mailbox control/status register definition bit # description 3C0 incoming mailbox full (msb:lsb) (r/wc) 7C4 outgoing mailbox full (msb:lsb) (r/wc) 11C8 reserved 12 incoming mailbox pci interrupt pending (r/wc) 13 outgoing mailbox pci interrupt pending (r/wc) 14 incoming mailbox dsp interrupt pending (r/wc) 15 outgoing mailbox dsp interrupt pending (r/wc) 16 incoming mailbox pci interrupt enable (r/w) 17 outgoing mailbox pci interrupt enable (r/w) 18 incoming mailbox dsp interrupt enable (r/w) 19 outgoing mailbox dsp interrupt enable (r/w) 31C20 reserved analog codec interface control/status register: bit # description 0 analog codec interface enable 1 analog codec reset disable 2 audio stream output enable 3 ad1819/ ac 97 mode 5C4 ad1819 dsp audio output control 6 ad1819 modem i/o enable 7 ad1819 handset i/o enable 8 force sdata_out high 9 force sync high 14C10 reserved 15 analog codec ready status (ro) legacy audio control/status register: bit # description 0 midi interrupt enable 1 subsystem id write enable 3C2 reserved 5C4 music synthesizer test mode 6 reserved 7 midi interrupt pending (ro)
AD1818 C19C rev. 0 preliminary technical data analog/digital interface analog/digital ac 97 protocol for complete information on ac 97, please refer to the analog devices ad1819 data sheet. ac 97 incorporates a 5-pin digital serial interface that links it to the AD1818. ac link is a bidirectional, fixed rate, serial pcm digital stream. it handles multiple input and output audio streams, as well as control register accesses employing a time division multiplexed (tdm) scheme. the ac link architecture divides each audio frame into 12 outgoing and 12 incoming data streams, each with 20-bit sample resolution. the AD1818 provides and accepts data with 16-bit resolution. synchronization of all ac link data transactions is signaled by the AD1818. the ac 97 codec drives the serial bit clock onto the ac link, which the AD1818 then qualifies with a synchro- nization signal to construct audio frames. sync, fixed at 48 khz, is derived by dividing down the serial bit clock (bit_clk). bit_clk, fixed at 12.288 mhz, provides the necessary clocking granularity to support 12, 20-bit outgoing and incoming time slots. ac link serial data is transitioned on each rising edge of bit_clk. the receiver of ac link data, the ac 97 codec for outgoing data and the AD1818 for incoming data, samples each serial bit on the falling edges of bit_clk. the ac link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a valid tag for its correspond- ing time slot within the current audio frame. a 1 in a given bit position of slot 0 indicates that the corresponding time slot within the current audio frame has been assigned to a data stream and contains valid data. if a slot is tagged, it is the responsibility of the source of the data for that slot (the ac 97 codec for the input stream, digital controller for the output stream) to stuff all bit positions with 0s during that slots active time. sync remains high for a total duration of 16 bit_clks at the beginning of each audio frame. the portion of the audio frame where sync is high is defined as the tag phase. the remainder of the audio frame where sync is low is defined as the data phase. additionally, for power savings, all clock, sync and data signals can be halted. this requires that the ac 97 codec be imple- mented as a static design to allow its register contents to remain intact when entering a power savings mode. ac link audio output stream (sdata_out) the audio output frame data streams correspond to the multi- plexed bundles of all digital output data targeting the ac 97s dac inputs and control registers. as briefly mentioned earlier, each audio frame supports up to twelve 20-bit outgoing data time slots. slot 0 is a special reserved time slot containing 16 bits used for ac link protocol infr astructure. within slot 0, the first bit is a global bit (sdata_out slot 0 bit 15) that flags the validity of the entire audio frame. if the valid frame bit is a 1, this indicates that the current audio frame contains at least one slot time of valid data. the next 12-bit position sampled by the ac 97 indicates which of the corresponding 12 time slots contain valid data. in this way, data streams of differing sample rates can be transmitted across link at its fixed 48 khz sync rate. figure 8 illustrates the time- slot- based ac link protocol. a new audio output frame begins with a low to high transi- tion of sync (see figure 9). sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the ac 97 samples the assertion of sync. this falling edge marks the time when both sides of the ac link are aware of the start of a new audio frame. on the next rising of bit_clk, the ac 97 controller transitions sdata_out into the first bit position of slot 0 (valid frame bit). each new bit position is presented to the ac link on a rising edge of bit_clk, and subsequently sampled by the ac 97 on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. sdata_outs composite stream is msb justified (msb first) with all nonvalid slots bit positions stuffed with 0s by the AD1818. for all valid slots, the AD1818 provides 16 valid data bits and stuffs 0s in the nonvalid trailing bit positions. slot 1: command address port the command port is used to control fractures, and monitor status (see audio input frame slots 1 and 2) for ac 97 functions including, but not limited to, mixer settings and power management. the control interface architecture supports up to 64 16-bit read/write registers. audio output frame slot 1 stream communicates control register address and write/read com- mand information to the ac 97. tag phase data phase 20? (48khz) valid frame end of previous audio frame time slot "valid" bits ("1" = time slot contains valid pcm data) slot 1 slot 2 slot 3 slot 12 slot(2) slot(12) slot(1) "0" "0" "0" 19 19 00 19 19 0 0 sync bit_clk sdata_out 12.288mhz 81.4ns figure 8. time-slot-based ac link protocol
AD1818 C20C rev. 0 preliminary technical data command address port bit assignments: bit (19) write/read command (1 = read, 0 = write) bit (18:12) control register index (64 16-bit locations, addressed on even byte boundaries) bit (11:0) reserved (stuffed with 1s) the first bit (msb) sampled by the ac 97 indicates whether the current control transaction is a read or write operation. the following seven-bit positions communicate the targeted control register address. the trailing 12-bit positions within the slot are reserved and are stuffed with 0s by the AD1818. slot 2: command data port the command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle (as indicated by slot 1 bit 19). command data port bit assignments: bit (19:4) control register write data (stuffed with 0s if cur- rent operation is a read) bit (3:0) reserved (stuffed with 0s) slots 3C12: data input channels slots 3 through 12 are data input channels assigned to audio or modem streams as defined by the analog codec interface control/ status register in the AD1818. each slot is defined as follows: data output bit assignments: bit (19:4) output data (stuffed with 0s if current slot is invalid) bit (3:0) reserved (stuffed with 0s) ac link audio input stream (sdata_in) the audio input frame data streams correspond to the multiplexed bundles of all digital input data targeting the AD1818. as in the case for the audio output stream, each ac link audio input frame consists of 12 20-bit time slots. slot 0 is a special reserved time slot containing 16 bits used for ac link protocol infrastruc ture. within slot 0, there is a global bit (sdata_out slot 0 bit 15), which flags whether the ac 97 is in the codec ready state or not. if the codec ready bit is a 0, this indicates that the ac 97 is not ready for normal operation. this condition is normal following the deassertion of power on reset, for example, while the ac 97s voltage references settle. when the ac link codec ready indicator bit is a 1, it indicates an ac 97 control. if the valid frame bit is a 1, this indicates that the current audio f rame contains at least one slot time of valid data. the next 12-bit position sampled by the ac 97 indicates which of the corresponding 12 time slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac link at its fixed 48 khz sync rate. figure 8 illustrates the time-slot-based ac link protocol. if the ac 97 is sampled codec ready, the next 12-bit positions sampled by the AD1818 indicate which of the corresponding 12 audio input slots contain valid data. in this way data streams of differing sample rates can be transmitted across ac link at its fixed 48 khz sync rate. a new audio input frame begins with a low-to-high transition of sync. sync is synchronous to the rising edge of bit_clk. on the immediately following falling edge of bit_clk, the ac 97 samples the assertion of sync. this falling edge marks the time when both sides of ac link are aware of the start of a new audio frame. on the next rising edge of bit_clk, the ac 97 transitions sdata_in into the first bit position of slot 0 (codec ready bit). each new bit position is presented to ac link on a rising edge of bit_clk, and subsequently sampled by the ac 97 controller on the following falling edge of bit_clk. this sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned. valid frame slot(2) slot(1) end of previous audio frame sync bit_clk sdata_out ac '97 samples sync assertion here ac '97 samples first sdata_out bit of frame here figure 9. start of an audio output frame sdata_ins composite stream is msb justified (msb first) with all nonvalid bit positions stuffed with 0s by the ac 97. sdata_in data is sampled on the falling edges of bit_clk . slot 1: status address port the status port is used to monitor status for ac 97 functions including, but not limited to, mixer settings, and power management. audio input frame slot 1s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (assu ming that slots 1 and 2 had been tagged valid by the ac 97 during slot 0.) status address port bit assignments: bit (19) reserved (stuffed with 0s) bit (18:12) control register index (echo of register index for w hich data is being returned) bit (11:0) reserved (stuffed with 0s) the first bit (msb) generated by the ac 97 is always stuffed with a 0. the following seven bit positions communicate the associated control register address and the trailing 12 bit positions are stuffed with 0s by the ac 97. slot 2: status data port the status data port delivers 16-bit control register read data. status data port bit assignments: bit (19:4) control register read data (stuffed with 0s if tagged invalid by the ac 97) bit (3:0) reserved (stuffed with 0s) slots 3C12: data input channels slots 3 through 12 are data input channels assigned to audio or modem streams as defined by the analog codec interface control/status register in the AD1818. each slot is defined as follows: data input bit assignments: bit (19:4) input data (stuffed with 0s if tagged invalid by the ac 97) bit (3:0) reserved (stuffed with 0s)
AD1818 C21C rev. 0 preliminary technical data analog codec interface control there are several configurations in which the analog codec interface can work. these configurations are controlled by the bits in the analog codec interface control/status register. bits in this register enable and reset the interface and control data transfers to an ad1819 or other ac 97 compatible codec. the register can be accessed from the host through the pci interface and from the dsp. this register is shown below: analog codec interface control/status register: bit 0 analog codec interface enable bit 1 analog codec reset disable bit 2 audio stream output enable bit 3 ad1819/ac 97-mode bit 5:4 ad1819 dsp audio output control bit 6 ad1819 modem i/o enable bit 7 ad1819 handset i/o enable bit 8 force sdata_out high bit 9 force sync high bit 15 analog codec ready status (ro) the codec interface enable (bit 0) is the primary enable for the AD1818 interface to the ac link. setting this bit will turn on interface to use the external bit_clk signal com ing in on the link. therefore, bit 0 should be enabled after reset on the ac link has been disabled by setting bit 1 in this register. turning on this bit will pull the reset# pin high (inactive) on the ac link, thus enabling the bit_clk outputs on the ac 97 codec. once the interface is out of reset and enabled, the codec should be ready before any data or control words are sent to the codec. the AD1818 monitors the codec ready status of the interface and reflects it in bit 15 of this register. this status signal is also available to the dsp as flag input bit 5. codec ready going high (active) signals that register transactions between the AD1818 and the codec can occur. registers on the codec can be written and read by the host through the pci interface and by the dsp. the codec registers are seen by the host at memory locations 0x1000 to 0x107f offset from base address register 0. these registers are accessible from the dsp on i/o page 0x10, locations 0x00 to 0x7f. once the codec has been enabled and the mode of operation set, data can begin to be sent to the interface. for st andard ac 97 operation, the audio stream output enable should be set and the ad1819/ac 97-mode bit left low. with the audio stream output enable set, data from the primary summer mixer output will be sent to the codec at a 48 khz sample rate. for extended functionality when using multiple ad1819 codecs, bits 3 through 7 in the analog codec interface control register are used to control the system setup. with multiple ad1819 codecs, AD1818 can be programmed to send six channels of audio for surround sound (3 ad1819s), or two audio channels plus modem data and handset channels (two ad1819s), or other combinations. overall ad1819 operating modes are enabled by setting the ad1819 mode (bit 3) high. this enables all of the rest of the control bits associated with the ad1819. in ad1819 mode, there are two potential sources of audio data: the primary summer mixer output or the dsp via fifo #2. mixer output is enabled by setting the audio stream output enable bit. if the dsp is to generate the audio data, then the audio stream output enable bit should be low and the ad1819 dsp audio output control (bits 5-4) used to control the number of audio channels to be shipped to the ad1819s as shown below: bits 5:4 # of 1819 dsp audio channels 00 no audio channels (use mixer if enabled) 01 2 audio channels from dsp to ad1819 10 4 audio channels from dsp to ad1819 11 6 audio channels from dsp to ad1819 bits 6 and 7 in the analog codec interface control register control the ad1819 modem and handset i/o enables, respectively. modem and handset data generally is shipped to and from the dsp to the codec interface. control bits in the dsp to mixer fifos control which fifos send and receive the modem and handset data. when multiple ad1819s are used in a system with the AD1818, there are requirements on the functionality performed by the master ad1819. (see the ad1819 data sheet for more information on codec master and slave organization.) when mixer audio output is enabled, audio data is shipped on the first two data channels in each frame, thus the master codec must be used as the audio codec. any modem data would be transferred on later channels, and thus the modem must be the slave codec. when the dsp is used to supply audio data, however, the modem data is shipped in the first two channels, therefore going to the master codec. the dsp can ship two or four channels of audio when modem is enabled. these channels will go in successive slots to slave codecs 1 or 2. bits 8 and 9 in the analog codec interface control register are used for test modes to control the sync and sdata_out pins. for normal operation they must be cleared.
AD1818 C22C rev. 0 preliminary technical data electrical specifications write data idle idle x 12 3 c = command type be = byte enables a = address pa = parity c & a d = data pd = parity be & d clk frame# irdy# c/be# ad trdy# devsel# par c a be pa pd d x add figure 10. slave single write access cycle (medium speed decode) read data idle add idle x 12 3x c = command type be = byte enables a = address pa = parity c & a d = data pd = parity be & d clk frame# irdy# c/be# ad trdy# devsel# par c a be pa pd d figure 11. slave single read access cycle (medium speed decode)
AD1818 C23C rev. 0 preliminary technical data c = command type be = byte enables a = address pa = parity c & a d = data pd = parity be & d c a be d idle microaccesses data add idle init. sub sub sub 1 2 3 4 n ?1 n x x clk frame# irdy# c/be# ad trdy# devsel# x par dd d be be be pa pd pd pd pd figure 12. master burst read access cycle idle write add data idle idle read data idle c = command type be = byte enables a = address pa = parity c & a d = data pd = parity be & d clk frame# irdy# c/be# ad trdy# devsel# par 12x x x x 12 3 add cbe ad pa pd be c ad pa pd figure 13. master single write and read access cycle
AD1818 C24C rev. 0 preliminary technical data absolute maximum ratings* min typ max units power supplies digital (dv dd ) C0.3 6.0 v analog (av dd ) C0.3 6.0 v input current (except supply pins) 10.0 ma analog input voltage (signal pins) av dd + 0.3 v digital input voltage (signal pins) dv dd + 0.3 v ambient temperature (operating) 0 +70 c storage temperature C65 +150 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. clock specifications* min typ max units input crystal/clock frequency 33 mhz input clock duty cycle (when an external clock is used instead of a crystal) 25/75 75/25 % initialization sample rate change time (neglecting pipeline delay of 1/4 sample period) 0 ns *guaranteed, not tested. package characteristics typ units pqfp q ja (thermal resistance [junction-to-ambient]) tbd c/w pqfp q jc (thermal resistance [junction-to-case]) tbd c/w idle add idle data init. sub sub sub sub c a d be pa pd be be be be dddd pd pd pd pd c = command type be = byte enables a = address pa = parity c & a d = data pd = parity be & d clk frame# irdy# c/be# ad trdy# devsel# par stop# microaccesses 1234 x x n? n x figure 14. master burst write access cycle
AD1818 C25C rev. 0 preliminary technical data ac specifications for 5 v signaling symbol parameter condition min max units notes i oh(ac) switching 0 < v out 1.4 C44 ma 1 current high 1.4 < v out < 2.4 C44 + (v out C 1.4)/0.024 ma 1, 2 3.1 < v out < v cc equation a 1, 3 (test point) v out = 3.1 C142 ma 3 i ol(ac) switching v out 3 2.2 95 ma 1 current low 2.2 < v out < 0.55 v out /0.023 ma 1 0.71 < v out < 0 equation b 1, 3 (test point) v out = 0.71 206 ma 3 i cl low clamp current C5 < v in C1 C25 + (v in + 1)/0.015 ma slew r output rise slew rate 0.4 v to 2.4 v load 1 5 v/ns 4 slew f output fall slew rate 2.4 v to 0.4 v load 1 5 v/ns 4 notes 1. refer to the v/i curves in figure 4-3. switching current characteristics for req# and gnt# are permitted to be one half of that specified here; i.e., half size output drivers may be used on these signals. this specification does not apply to clk and rst#, which are system outputs. switching current high specifica- tions are not relevant to serr# , inta# , intb# , intc# and intd#, which are open drain outputs. 2. note that this segment of the minimum current curve is drawn from the ac drive point directly to the dc drive point rather th an toward the voltage rail (as is done in the pull-down curve). this difference is intended to allow for an optional n-channel pull-up. 3. maximum current requirements must be met as drivers pull beyond the first step voltage. equations defining these maximums (a and b) are provided with the respective diagrams in figure 4-3. the equation defined maxima should be met by design. in order to facilitate component testin g, a maximum current test point is defined for each side of the output driver. dc specifications for 5 v signaling symbol parameter condition min max units notes v cc supply voltage 4.75 5.25 v v ih input high voltage 2.0 v cc + 0.5 v v il input low voltage C0.5 0.8 v i ih input high leakage current v in = 2.7 70 m a1 i il input low leakage current v in = 0.5 C70 m a1 v oh output high voltage i out = C2 ma 2.4 v v ol output low voltage i out = 3 ma, 6 ma 0.55 v 2 c in input pin capacitance 10 pf 3 c clk clk pin capacitance 5 12 pf c idsel idsel pin capacitance 8 pf 4 l pin pin inductance 20 nh notes 1. input leakage currents include hi-z output leakage for all bidirectional buffers with three-state outputs. 2. signals without pull-up resistors must have 3 ma low output current. signals requiring pull-up must have 6 ma; the latter inc lude, frame# , trdy# , irdy# , devsel# , stop# , serr# , perr# , lock# and, when used, ad[63::32] , c/be[7::4# , par64 , req64# , and ack64# . 3. absolute maximum pin capacitance for a pci input is 10 pf (except for clk ) with an exception granted to motherboard-only devices, which could be up to 16 pf, in order to accommodate pga packaging. this would mean, in general, that components for expansion boards would need to u se alternatives to ceramic pga packaging (i.e., pqfp, sga, etc.). 4. lower capacitance on this input only pin allows for nonresistive coupling to ad[xx] .
AD1818 C26C rev. 0 preliminary technical data application circuits figure 15. bit clk nc nc nc vss nc vcc sda scl u7 x24c01s 1k (128x8-bit) eeprom 1 2 3 45 6 7 8 c35 100nf dvdd r24 20k w r25 20k w y2 33mhz 3rd ot c3 22pf np0 c4 22pf np0 r28 47r5 c45 270pf np0 l1 2 2 r20 4k99 tdo btdi btrst btck btms pci bus interface key jp4 jtag/emulation header pci bus jumpers in place tms tck trst tdi ac97 i/f daa i/f midi interface j7 dvdd 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 fb12 600z fb13 600z r19 4k99 sync sdata in sdata out 78 77 76 75 74 72 73 32 40 35 45 37 34 38 33 31 25 26 27 28 24 23 21 22 42 43 midi_in midi_out bit_clk sync sdata_in sdata_in ring hook phone micena xctl0 xctl1 flag0 flag1 eck ems edi edo emu scl sda xtali/clkin xtalo dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd dvdd 13 20 30 44 49 52 63 81 84 97 108 116 121 3 dvdd c23 100nf c24 100nf c25 100nf c26 100nf c27 100nf c28 100nf c29 100nf c30 100nf c31 100nf c32 100nf c33 100nf c34 100nf clk ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ad10 ad11 ad12 ad13 ad14 ad15 ad16 ad17 ad18 ad19 ad20 ad21 ad22 ad23 ad24 ad25 ad26 ad27 ad28 ad29 ad30 ad31 par idsel dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd dgnd 8 18 19 39 41 51 57 68 71 83 92 103 113 115 126 u6 AD1818js 85 82 16 14 11 9 5 2 128 125 109 106 104 101 96 94 91 89 98 123 122 111 112 99 87 119 80 15 12 10 7 4 1 127 124 107 105 102 100 95 93 90 88 110 6 114 118 117 86 120 79 b16 a15 a58 a57 a55 a54 b52 b48 b47 b45 a32 a31 a29 a28 a25 a23 a22 a20 b26 b44 a43 a34 b35 a26 b18 b40 a6 b58 b56 b55 b53 a49 a47 a46 a44 b32 b30 b29 b27 b24 b23 b21 b20 b33 a52 a36 b37 b42 a19 a38 a17 a41 a40 b2 a4 a1 b9 a3 b4 b11 sdone btck etms btdi tdo btrst 5v/32-bit pci bus board interface pinout dvdd (+5v) = a(5,8,10,16,58,61,62), b(5,6,19,58,61,62) dgnd (ground) = a(12,13,18,24,30,35,37,42,48,56), b(3,12,13,15,17,22,28,34,38,46,49,57) pci i/f notes: trace lengths < 1.5"(38.1mm) clk trace = 2.5" 0.1"(63.5mm) z o = 80 20 w v pd = 170 20 ps/in dvdd
AD1818 C27C rev. 0 preliminary technical data figure 16.
AD1818 C28C rev. 0 preliminary technical data figure 17.
AD1818 C29C rev. 0 preliminary technical data 128-terminal metric plastic quad flatpack (pqfp) (s-128a) top view (pins down) 0.011 (0.27) 0.007 (0.17) 0.555 (14.10) 0.547 (13.90) 0.792 (20.10) 0.783 (19.90) 1 38 39 65 64 102 128 103 0.685 (17.40) 0.669 (17.00) 0.921 (23.40) 0.906 (23.00) 1.27 (0.50) bsc seating plane 0.134 (3.40) max 0.041 (1.03) 0.031 (0.78) 0.003 (0.08) max 0.110 (2.80) 0.102 (2.60) 0.010 (0.25) min outline dimensions dimensions shown in mm and (inches). rev. 0

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